1. Field of Invention
The present invention relates to a binary counter and, more specifically, to a counter for counting up, counting down or for counting up and down binary data.
FIG. 8 is a block diagram illustrating structures of a conventional updown counter which is disclosed in "Principles of CMOS VLSI Design" 1985 by AT&T Bell Laboratories, p. 338. An example shown in FIG. 8 is the updown counter of 3 bits. In the Figure, this updown counter comprises selectors 1b and 1c, adders 2a-2c and flip-flops 3a-3c. Each of the selectors 1b and 1c has one input terminal A connected to a power source. The other input terminal B of each of the selectors 1b and 1c is connected to the ground. The selectors 1b and 1c are responsive to up/down control signals inputted to selector control terminals S to selectively output the inputs applied to the input terminals A or the inputs applied to the input terminals B from the output terminals Y, respectively. Thus, when a command for a down-count mode is applied by the up/down control signals to the selectors 1b and 1c, they select and output the inputs applied to the input terminals A, and when the command for an up-count mode is applied, the inputs applied to the input terminals B are selected and outputted. One input terminal A of each of the adders 2a-2c receives outputs from Q output terminals of the flip-flops 3a-3c, respectively. The other terminal B of each of the adders 2b and 2c receives the outputs from the selectors 1b and 1c. The input terminal B of the adder 2a is fixedly connected to the power source. The adders 2a-2c add values inputted to the input terminals A with values inputted to the input terminals B, and output the resultant sum from sum signal output terminals S, respectively. When a carry is generated as a result of the addition, the adders 2a-2 c output carry signals from carry output terminals CO, respectively. The carry signals outputted from the adders 2a and 2b are applied to carry input terminals Ci of the adders 2b and 2c at a next stage in a more significant bit side. A carry input terminal of the adder 2a for a least significant bit is grounded. The sum signal output terminals S of the adders 2a-2c are connected to data input terminals D of the flip-flops 3a-3c, respectively. The flip-flops 3a-3c are responsive to rising edges (or falling edges) of clock signals applied to clock terminals CK to capture the signals applied to the data input terminals D and store the same. The stored data in the flip-flops 3c are outputted from Q output terminals and are applied to output terminals 4a-4c, respectively. Outputs from these output terminals 4a-4c form an output from the updown counter.
Operations of the updown counter thus constructed and shown in FIG. 8 will be described below. When the up-count mode is commanded by the up/down control signal, the selectors 1b and 1c select the input through the input terminals B for outputting them, so that a binary data "001" (=+1) is inputted to each of the flip-flops 2a-2c. Therefore, the updown counter in this case functions as the up-counter which adds one to the data stored in the flip-flops 3a and 3d. On the other hand, when the down-count mode is commanded by the up/down control signal, the selectors 1b and 1c select the input terminals A for outputting, so that the binary data "111" is inputted to the flip-flops 2a-2c. If the binary data "111" is a binary data of 3 bits represented by the complement on two, it represents minus one (-1). Therefore, the addition of "111" to the original binary data stored in the flip-flops 3a-3c is equal to addition of minus one, i.e., subtraction of one. In this case, the updown counter functions as the down-counter.
If the adders 2a-2c in FIG. 8 have well known Manchester structures as shown in FIG. 9, each adder requires 24 transistors. The selectors 1b and 1c each can be formed by four transistors, and the flip-flops 3a-3c each can be formed by 16 transistors. Therefore, the conventional updown counter shown in FIG. 8 requires 44 transistors per one stage. Thus, the conventional updown counter shown in FIG. 8 requires many transistors, which unpreferably increases a circuit area and a cost.
The above described problem occurs not only in such updown counters as shown in FIG. 8 but also in general binary counters (up counter, down counter and updown counter) counting binary data.